// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  CLK_DIV
// 12'h004  CLK_GATE_APB
// 12'h00C  CLK_GATE_AHB
// 12'h014  SYSTEM_SOFTWARE_RESET
// 12'h01C  MODULE_SW_RESET_APB
// 12'h024  MODULE_SW_RESET_AHB
// 12'h040  PLL_CFG1
// 12'h044  PLL_CFG2
// 12'h048  PLL_DBG
// 12'h060  CIR
// 12'h070  EXTAL_CFG
// 12'h108  RST_REASON
// 12'h110  LDO1P5_CFG
// 12'h118  LDO5P0_CFG
// 12'h11C  BG_OTP_CFG
// 12'h120  VT_RST_ENABLE
// 12'h124  INT_STATUS
// 12'h128  INT_ENABLE
// 12'h12C  INT_CLEAR
// 12'h130  BIAS_CFG
// 12'h200  SSC_CFG
// 12'h180  CLK_MUX
// -FHDR
// ---------------------------------------------------------------

module rcc_regfile (
    output [03:0]          clk_div_clk_div_factor,
    output [01:0]          clk_div_clksel      ,
    output [01:0]          clk_div_pclk_div    ,
    output                 clk_div_css_en      ,
    input                  clk_div_css_flag    ,
    output                 clk_gate_apb_clk_en_uart0,
    output                 clk_gate_apb_clk_en_tim2,
    output                 clk_gate_apb_clk_en_tim1,
    output                 clk_gate_apb_clk_en_tim0,
    output                 clk_gate_apb_clk_en_sysctrl,
    output                 clk_gate_apb_clk_en_adc0,
    output                 clk_gate_apb_clk_en_adc1,
    output                 clk_gate_apb_clk_en_spi0,
    output                 clk_gate_apb_clk_en_spi1,
    output                 clk_gate_apb_clk_en_epwm,
    output                 clk_gate_apb_clk_en_ecap,
    output                 clk_gate_apb_clk_en_ediag,
    output                 clk_gate_apb_clk_en_can,
    output                 clk_gate_apb_clk_en_iwdg,
    output                 clk_gate_apb_clk_en_dflash,
    output                 clk_gate_ahb_clk_en_gpio,
    output                 clk_gate_ahb_clk_en_dma,
    output                 clk_gate_ahb_clk_en_esci,
    output                 system_software_reset_sys_sw_rst,
    output [07:0]          system_software_reset_sys_sw_rst_en,
    output                 module_sw_reset_apb_sw_rst_wwdg,
    output                 module_sw_reset_apb_sw_rst_uart0,
    output                 module_sw_reset_apb_sw_rst_tim2,
    output                 module_sw_reset_apb_sw_rst_tim1,
    output                 module_sw_reset_apb_sw_rst_tim0,
    output                 module_sw_reset_apb_sw_rst_sysctrl,
    output                 module_sw_reset_apb_sw_rst_adc0,
    output                 module_sw_reset_apb_sw_rst_adc1,
    output                 module_sw_reset_apb_sw_rst_spi0,
    output                 module_sw_reset_apb_sw_rst_spi1,
    output                 module_sw_reset_apb_sw_rst_epwm,
    output                 module_sw_reset_apb_sw_rst_ecap,
    output                 module_sw_reset_apb_sw_rst_ediag,
    output                 module_sw_reset_apb_sw_rst_can0,
    output                 module_sw_reset_apb_sw_rst_iwdg,
    output                 module_sw_reset_apb_sw_rst_dflash,
    output                 module_sw_reset_ahb_sw_rst_gpio,
    output                 module_sw_reset_ahb_sw_rst_dma,
    output                 module_sw_reset_ahb_sw_rst_esci,
    output                 pll_cfg1_pll_en     ,
    input                  pll_cfg1_pll_stable ,
    output                 pll_cfg1_pll_ref_sel,
    output [01:0]          pll_cfg1_pll_postdiv,
    output [01:0]          pll_cfg1_pll_prediv ,
    output [07:0]          pll_cfg1_pll_loopdiv,
    output [01:0]          pll_cfg1_pll_ref_div,
    output                 pll_cfg2_pll_lpf_c  ,
    output [02:0]          pll_cfg2_pll_lpf_rsel,
    output                 pll_cfg2_pll_kvco   ,
    output                 pll_cfg2_pll_ccoband,
    output [03:0]          pll_cfg2_pll_icp    ,
    output [09:0]          pll_cfg2_pll_ckusable_divsel,
    output [02:0]          pll_cfg2_pll_ldovrefsel,
    output [02:0]          pll_dbg_pll_dig_dbg ,
    output [02:0]          pll_dbg_pll_ana_dbg ,
    input                  pll_dbg_pll_dbg_out ,
    output                 cir_pll_ie          ,
    input                  cir_pll_stablt_int_flag,
    output           cir_pll_stablt_int_clr,
    output                 extal_cfg_in_en     ,
    output                 extal_cfg_out_en    ,
    output [02:0]          extal_cfg_stg       ,
    input  [03:0]          rst_reason_rst_reason_status,
    output                 ldo1p5_cfg_d2a_uv15_en,
    output                 ldo1p5_cfg_d2a_ov15_en,
    output [02:0]          ldo1p5_cfg_d2a_uv15_level,
    output [02:0]          ldo1p5_cfg_d2a_ov15_level,
    output                 ldo5p0_cfg_d2a_uv50_en,
    output                 ldo5p0_cfg_d2a_ov50_en,
    output                 ldo5p0_cfg_d2a_en_test_avdd50_div,
    output [02:0]          ldo5p0_cfg_d2a_uv50_level,
    output [02:0]          ldo5p0_cfg_d2a_ov50_level,
    output                 bg_otp_cfg_d2a_otp_en,
    output                 bg_otp_cfg_d2a_bg_bf_en,
    output [03:0]          bg_otp_cfg_d2a_otp_sel,
    output                 vt_rst_enable_ov15_rst_en,
    output                 vt_rst_enable_uv15_rst_en,
    output                 vt_rst_enable_otp_rst_en,
    output                 vt_rst_enable_ov50_rst_en,
    output                 vt_rst_enable_uv50_rst_en,
    output                 vt_rst_enable_bg_otp_rst_en,
    output                 vt_rst_enable_ldo15oc_rst_en,
    output                 vt_rst_enable_iwdg  ,
    input                  int_status_ov15_lv  ,
    input                  int_status_uv15_lv  ,
    input                  int_status_ov50_lv  ,
    input                  int_status_uv50_lv  ,
    input                  int_status_bg_otp_lv,
    input                  int_status_ldo15oc_otp_lv,
    output                 int_enable_ov15_int_en,
    output                 int_enable_uv15_int_en,
    output                 int_enable_ov50_int_en,
    output                 int_enable_uv50_int_en,
    output                 int_enable_bg_otp_int_en,
    output                 int_enable_ldp15oc_int_en,
    output           int_clear_ov15_int_clr,
    output           int_clear_uv15_int_clr,
    output           int_clear_ov50_int_clr,
    output           int_clear_uv50_int_clr,
    output           int_clear_bg_otp_int_clr,
    output           int_clear_ldo15oc_int_clr,
    output                 bias_cfg_d2a_ibias_en,
    output [01:0]          ssc_cfg_ssc_mode    ,
    output                 ssc_cfg_ssc_en      ,
    output [03:0]          ssc_cfg_ssc_freq_step,
    output [03:0]          ssc_cfg_ssc_freq_range,
    output [06:0]          ssc_cfg_ssc_freq_stay,
    output                 clk_mux_osc_dbg_sel ,
    output                 clk_mux_lin_baud_clk_sel,
    output [01:0]          clk_mux_dbg_clk_sel ,
    output [01:0]          clk_mux_adc_div     ,
    output           clk_mux_adc_div_up  ,
    output                 clk_mux_adc_clk_sel ,
    input                  pclk                ,
    input                  prstn               ,

    input                  psel                ,
    input  [11:0]          paddr               ,
    input                  penable             ,
    input                  pwrite              ,
    input  [31:0]          pwdata              ,
//    output                pready              ,
//    output                pslverr             ,
    output [31:0]          prdata
);

// ------------------------------------------------------------
// APB write read enable
// ------------------------------------------------------------
reg     [31:0]  ff_rdata;
wire            read_en   = psel && (~penable) && (~pwrite);
wire            write_en  = psel && (~penable) && pwrite;
wire    [11:0]  addr      = paddr;
wire    [31:0]  wdata     = pwdata;

always @(posedge pclk or negedge prst) begin
    if (!prst)
        prdata <= 32'b0;
    else if (read_en) 
        prdata <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------
reg     [03:0]  ff_clk_div_clk_div_factor;
reg     [01:0]  ff_clk_div_clksel   ;
reg     [01:0]  ff_clk_div_pclk_div ;
reg             ff_clk_div_css_en   ;
reg             ff_clk_gate_apb_clk_en_uart0;
reg             ff_clk_gate_apb_clk_en_tim2;
reg             ff_clk_gate_apb_clk_en_tim1;
reg             ff_clk_gate_apb_clk_en_tim0;
reg             ff_clk_gate_apb_clk_en_sysctrl;
reg             ff_clk_gate_apb_clk_en_adc0;
reg             ff_clk_gate_apb_clk_en_adc1;
reg             ff_clk_gate_apb_clk_en_spi0;
reg             ff_clk_gate_apb_clk_en_spi1;
reg             ff_clk_gate_apb_clk_en_epwm;
reg             ff_clk_gate_apb_clk_en_ecap;
reg             ff_clk_gate_apb_clk_en_ediag;
reg             ff_clk_gate_apb_clk_en_can;
reg             ff_clk_gate_apb_clk_en_iwdg;
reg             ff_clk_gate_apb_clk_en_dflash;
reg             ff_clk_gate_ahb_clk_en_gpio;
reg             ff_clk_gate_ahb_clk_en_dma;
reg             ff_clk_gate_ahb_clk_en_esci;
reg             ff_system_software_reset_sys_sw_rst;
reg     [07:0]  ff_system_software_reset_sys_sw_rst_en;
reg             ff_module_sw_reset_apb_sw_rst_wwdg;
reg             ff_module_sw_reset_apb_sw_rst_uart0;
reg             ff_module_sw_reset_apb_sw_rst_tim2;
reg             ff_module_sw_reset_apb_sw_rst_tim1;
reg             ff_module_sw_reset_apb_sw_rst_tim0;
reg             ff_module_sw_reset_apb_sw_rst_sysctrl;
reg             ff_module_sw_reset_apb_sw_rst_adc0;
reg             ff_module_sw_reset_apb_sw_rst_adc1;
reg             ff_module_sw_reset_apb_sw_rst_spi0;
reg             ff_module_sw_reset_apb_sw_rst_spi1;
reg             ff_module_sw_reset_apb_sw_rst_epwm;
reg             ff_module_sw_reset_apb_sw_rst_ecap;
reg             ff_module_sw_reset_apb_sw_rst_ediag;
reg             ff_module_sw_reset_apb_sw_rst_can0;
reg             ff_module_sw_reset_apb_sw_rst_iwdg;
reg             ff_module_sw_reset_apb_sw_rst_dflash;
reg             ff_module_sw_reset_ahb_sw_rst_gpio;
reg             ff_module_sw_reset_ahb_sw_rst_dma;
reg             ff_module_sw_reset_ahb_sw_rst_esci;
reg             ff_pll_cfg1_pll_en  ;
reg             ff_pll_cfg1_pll_ref_sel;
reg     [01:0]  ff_pll_cfg1_pll_postdiv;
reg     [01:0]  ff_pll_cfg1_pll_prediv;
reg     [07:0]  ff_pll_cfg1_pll_loopdiv;
reg     [01:0]  ff_pll_cfg1_pll_ref_div;
reg             ff_pll_cfg2_pll_lpf_c;
reg     [02:0]  ff_pll_cfg2_pll_lpf_rsel;
reg             ff_pll_cfg2_pll_kvco;
reg             ff_pll_cfg2_pll_ccoband;
reg     [03:0]  ff_pll_cfg2_pll_icp ;
reg     [09:0]  ff_pll_cfg2_pll_ckusable_divsel;
reg     [02:0]  ff_pll_cfg2_pll_ldovrefsel;
reg     [02:0]  ff_pll_dbg_pll_dig_dbg;
reg     [02:0]  ff_pll_dbg_pll_ana_dbg;
reg             ff_cir_pll_ie       ;
reg       ff_cir_pll_stablt_int_clr;
reg             ff_extal_cfg_in_en  ;
reg             ff_extal_cfg_out_en ;
reg     [02:0]  ff_extal_cfg_stg    ;
reg             ff_ldo1p5_cfg_d2a_uv15_en;
reg             ff_ldo1p5_cfg_d2a_ov15_en;
reg     [02:0]  ff_ldo1p5_cfg_d2a_uv15_level;
reg     [02:0]  ff_ldo1p5_cfg_d2a_ov15_level;
reg             ff_ldo5p0_cfg_d2a_uv50_en;
reg             ff_ldo5p0_cfg_d2a_ov50_en;
reg             ff_ldo5p0_cfg_d2a_en_test_avdd50_div;
reg     [02:0]  ff_ldo5p0_cfg_d2a_uv50_level;
reg     [02:0]  ff_ldo5p0_cfg_d2a_ov50_level;
reg             ff_bg_otp_cfg_d2a_otp_en;
reg             ff_bg_otp_cfg_d2a_bg_bf_en;
reg     [03:0]  ff_bg_otp_cfg_d2a_otp_sel;
reg             ff_vt_rst_enable_ov15_rst_en;
reg             ff_vt_rst_enable_uv15_rst_en;
reg             ff_vt_rst_enable_otp_rst_en;
reg             ff_vt_rst_enable_ov50_rst_en;
reg             ff_vt_rst_enable_uv50_rst_en;
reg             ff_vt_rst_enable_bg_otp_rst_en;
reg             ff_vt_rst_enable_ldo15oc_rst_en;
reg             ff_vt_rst_enable_iwdg;
reg             ff_int_enable_ov15_int_en;
reg             ff_int_enable_uv15_int_en;
reg             ff_int_enable_ov50_int_en;
reg             ff_int_enable_uv50_int_en;
reg             ff_int_enable_bg_otp_int_en;
reg             ff_int_enable_ldp15oc_int_en;
reg       ff_int_clear_ov15_int_clr;
reg       ff_int_clear_uv15_int_clr;
reg       ff_int_clear_ov50_int_clr;
reg       ff_int_clear_uv50_int_clr;
reg       ff_int_clear_bg_otp_int_clr;
reg       ff_int_clear_ldo15oc_int_clr;
reg             ff_bias_cfg_d2a_ibias_en;
reg     [01:0]  ff_ssc_cfg_ssc_mode ;
reg             ff_ssc_cfg_ssc_en   ;
reg     [03:0]  ff_ssc_cfg_ssc_freq_step;
reg     [03:0]  ff_ssc_cfg_ssc_freq_range;
reg     [06:0]  ff_ssc_cfg_ssc_freq_stay;
reg             ff_clk_mux_osc_dbg_sel;
reg             ff_clk_mux_lin_baud_clk_sel;
reg     [01:0]  ff_clk_mux_dbg_clk_sel;
reg     [01:0]  ff_clk_mux_adc_div  ;
reg       ff_clk_mux_adc_div_up;
reg             ff_clk_mux_adc_clk_sel;

wire            wir_clk_div_css_flag;
wire            wir_pll_cfg1_pll_stable;
wire            wir_pll_dbg_pll_dbg_out;
wire            wir_cir_pll_stablt_int_flag;
wire    [03:0]  wir_rst_reason_rst_reason_status;
wire            wir_int_status_ov15_lv;
wire            wir_int_status_uv15_lv;
wire            wir_int_status_ov50_lv;
wire            wir_int_status_uv50_lv;
wire            wir_int_status_bg_otp_lv;
wire            wir_int_status_ldo15oc_otp_lv;
assign          wir_clk_div_css_flag= clk_div_css_flag    ;
assign          wir_pll_cfg1_pll_stable= pll_cfg1_pll_stable ;
assign          wir_pll_dbg_pll_dbg_out= pll_dbg_pll_dbg_out ;
assign          wir_cir_pll_stablt_int_flag= cir_pll_stablt_int_flag;
assign          wir_rst_reason_rst_reason_status= rst_reason_rst_reason_status[03:0];
assign          wir_int_status_ov15_lv= int_status_ov15_lv  ;
assign          wir_int_status_uv15_lv= int_status_uv15_lv  ;
assign          wir_int_status_ov50_lv= int_status_ov50_lv  ;
assign          wir_int_status_uv50_lv= int_status_uv50_lv  ;
assign          wir_int_status_bg_otp_lv= int_status_bg_otp_lv;
assign          wir_int_status_ldo15oc_otp_lv= int_status_ldo15oc_otp_lv;

// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------
wire     wren_clk_div        = write_en & (addr[11:2] == 10'h0);
wire     wren_clk_gate_apb   = write_en & (addr[11:2] == 10'h1);
wire     wren_clk_gate_ahb   = write_en & (addr[11:2] == 10'h3);
wire     wren_system_software_reset= write_en & (addr[11:2] == 10'h5);
wire     wren_module_sw_reset_apb= write_en & (addr[11:2] == 10'h7);
wire     wren_module_sw_reset_ahb= write_en & (addr[11:2] == 10'h9);
wire     wren_pll_cfg1       = write_en & (addr[11:2] == 10'h10);
wire     wren_pll_cfg2       = write_en & (addr[11:2] == 10'h11);
wire     wren_pll_dbg        = write_en & (addr[11:2] == 10'h12);
wire     wren_cir            = write_en & (addr[11:2] == 10'h18);
wire     wren_extal_cfg      = write_en & (addr[11:2] == 10'h1c);
wire     wren_ldo1p5_cfg     = write_en & (addr[11:2] == 10'h44);
wire     wren_ldo5p0_cfg     = write_en & (addr[11:2] == 10'h46);
wire     wren_bg_otp_cfg     = write_en & (addr[11:2] == 10'h47);
wire     wren_vt_rst_enable  = write_en & (addr[11:2] == 10'h48);
wire     wren_int_enable     = write_en & (addr[11:2] == 10'h4a);
wire     wren_int_clear      = write_en & (addr[11:2] == 10'h4b);
wire     wren_bias_cfg       = write_en & (addr[11:2] == 10'h4c);
wire     wren_ssc_cfg        = write_en & (addr[11:2] == 10'h80);
wire     wren_clk_mux        = write_en & (addr[11:2] == 10'h60);

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_div_clk_div_factor <= 4'h4;
    else if (wren_clk_div) begin
        ff_clk_div_clk_div_factor <= wdata[3:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_div_clksel <= 2'h0;
    else if (wren_clk_div) begin
        ff_clk_div_clksel <= wdata[6:5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_div_pclk_div <= 2'h0;
    else if (wren_clk_div) begin
        ff_clk_div_pclk_div <= wdata[9:8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_div_css_en <= 1'h0;
    else if (wren_clk_div) begin
        ff_clk_div_css_en <= wdata[13];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_uart0 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_uart0 <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_tim2 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_tim2 <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_tim1 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_tim1 <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_tim0 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_tim0 <= wdata[4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_sysctrl <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_sysctrl <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_adc0 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_adc0 <= wdata[7];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_adc1 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_adc1 <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_spi0 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_spi0 <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_spi1 <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_spi1 <= wdata[10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_epwm <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_epwm <= wdata[11];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_ecap <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_ecap <= wdata[12];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_ediag <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_ediag <= wdata[13];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_can <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_can <= wdata[15];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_iwdg <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_iwdg <= wdata[16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_apb_clk_en_dflash <= 1'h0;
    else if (wren_clk_gate_apb) begin
        ff_clk_gate_apb_clk_en_dflash <= wdata[17];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_ahb_clk_en_gpio <= 1'h0;
    else if (wren_clk_gate_ahb) begin
        ff_clk_gate_ahb_clk_en_gpio <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_ahb_clk_en_dma <= 1'h0;
    else if (wren_clk_gate_ahb) begin
        ff_clk_gate_ahb_clk_en_dma <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_gate_ahb_clk_en_esci <= 1'h0;
    else if (wren_clk_gate_ahb) begin
        ff_clk_gate_ahb_clk_en_esci <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_system_software_reset_sys_sw_rst <= 1'h0;
    else if (wren_system_software_reset) begin
        ff_system_software_reset_sys_sw_rst <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_system_software_reset_sys_sw_rst_en <= 8'h0;
    else if (wren_system_software_reset)
        ff_system_software_reset_sys_sw_rst_en <= wdata[31:24];
    else 
        ff_system_software_reset_sys_sw_rst_en <= 8'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_wwdg <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_wwdg <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_uart0 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_uart0 <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_tim2 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_tim2 <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_tim1 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_tim1 <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_tim0 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_tim0 <= wdata[4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_sysctrl <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_sysctrl <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_adc0 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_adc0 <= wdata[7];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_adc1 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_adc1 <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_spi0 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_spi0 <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_spi1 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_spi1 <= wdata[10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_epwm <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_epwm <= wdata[11];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_ecap <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_ecap <= wdata[12];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_ediag <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_ediag <= wdata[13];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_can0 <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_can0 <= wdata[15];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_iwdg <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_iwdg <= wdata[16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_apb_sw_rst_dflash <= 1'h0;
    else if (wren_module_sw_reset_apb) begin
        ff_module_sw_reset_apb_sw_rst_dflash <= wdata[17];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_ahb_sw_rst_gpio <= 1'h0;
    else if (wren_module_sw_reset_ahb) begin
        ff_module_sw_reset_ahb_sw_rst_gpio <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_ahb_sw_rst_dma <= 1'h0;
    else if (wren_module_sw_reset_ahb) begin
        ff_module_sw_reset_ahb_sw_rst_dma <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_module_sw_reset_ahb_sw_rst_esci <= 1'h0;
    else if (wren_module_sw_reset_ahb) begin
        ff_module_sw_reset_ahb_sw_rst_esci <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_en <= 1'h0;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_ref_sel <= 1'h0;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_ref_sel <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_postdiv <= 2'h0;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_postdiv <= wdata[5:4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_prediv <= 2'h0;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_prediv <= wdata[9:8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_loopdiv <= 8'h80;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_loopdiv <= wdata[23:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg1_pll_ref_div <= 2'h0;
    else if (wren_pll_cfg1) begin
        ff_pll_cfg1_pll_ref_div <= wdata[31:30];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_lpf_c <= 1'h1;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_lpf_c <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_lpf_rsel <= 3'h5;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_lpf_rsel <= wdata[3:1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_kvco <= 1'h1;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_kvco <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_ccoband <= 1'h1;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_ccoband <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_icp <= 4'h1;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_icp <= wdata[13:10];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_ckusable_divsel <= 10'h40;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_ckusable_divsel <= wdata[25:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_cfg2_pll_ldovrefsel <= 3'h0;
    else if (wren_pll_cfg2) begin
        ff_pll_cfg2_pll_ldovrefsel <= wdata[30:28];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_dbg_pll_dig_dbg <= 3'h0;
    else if (wren_pll_dbg) begin
        ff_pll_dbg_pll_dig_dbg <= wdata[2:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_pll_dbg_pll_ana_dbg <= 3'h0;
    else if (wren_pll_dbg) begin
        ff_pll_dbg_pll_ana_dbg <= wdata[18:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cir_pll_ie <= 1'h0;
    else if (wren_cir) begin
        ff_cir_pll_ie <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_cir_pll_stablt_int_clr <= 1'h0;
    else if (wren_cir)
        ff_cir_pll_stablt_int_clr <= wdata[16];
    else 
        ff_cir_pll_stablt_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_extal_cfg_in_en <= 1'h0;
    else if (wren_extal_cfg) begin
        ff_extal_cfg_in_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_extal_cfg_out_en <= 1'h0;
    else if (wren_extal_cfg) begin
        ff_extal_cfg_out_en <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_extal_cfg_stg <= 3'h0;
    else if (wren_extal_cfg)
        ff_extal_cfg_stg <= wdata[18:16];
    else 
        ff_extal_cfg_stg <= 3'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo1p5_cfg_d2a_uv15_en <= 1'h0;
    else if (wren_ldo1p5_cfg) begin
        ff_ldo1p5_cfg_d2a_uv15_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo1p5_cfg_d2a_ov15_en <= 1'h0;
    else if (wren_ldo1p5_cfg) begin
        ff_ldo1p5_cfg_d2a_ov15_en <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo1p5_cfg_d2a_uv15_level <= 3'h0;
    else if (wren_ldo1p5_cfg) begin
        ff_ldo1p5_cfg_d2a_uv15_level <= wdata[6:4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo1p5_cfg_d2a_ov15_level <= 3'h0;
    else if (wren_ldo1p5_cfg) begin
        ff_ldo1p5_cfg_d2a_ov15_level <= wdata[10:8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo5p0_cfg_d2a_uv50_en <= 1'h0;
    else if (wren_ldo5p0_cfg) begin
        ff_ldo5p0_cfg_d2a_uv50_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo5p0_cfg_d2a_ov50_en <= 1'h0;
    else if (wren_ldo5p0_cfg) begin
        ff_ldo5p0_cfg_d2a_ov50_en <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo5p0_cfg_d2a_en_test_avdd50_div <= 1'h0;
    else if (wren_ldo5p0_cfg) begin
        ff_ldo5p0_cfg_d2a_en_test_avdd50_div <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo5p0_cfg_d2a_uv50_level <= 3'h0;
    else if (wren_ldo5p0_cfg) begin
        ff_ldo5p0_cfg_d2a_uv50_level <= wdata[6:4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ldo5p0_cfg_d2a_ov50_level <= 3'h0;
    else if (wren_ldo5p0_cfg) begin
        ff_ldo5p0_cfg_d2a_ov50_level <= wdata[10:8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_bg_otp_cfg_d2a_otp_en <= 1'h0;
    else if (wren_bg_otp_cfg) begin
        ff_bg_otp_cfg_d2a_otp_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_bg_otp_cfg_d2a_bg_bf_en <= 1'h0;
    else if (wren_bg_otp_cfg) begin
        ff_bg_otp_cfg_d2a_bg_bf_en <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_bg_otp_cfg_d2a_otp_sel <= 4'h0;
    else if (wren_bg_otp_cfg) begin
        ff_bg_otp_cfg_d2a_otp_sel <= wdata[7:4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_ov15_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_ov15_rst_en <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_uv15_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_uv15_rst_en <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_otp_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_otp_rst_en <= wdata[4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_ov50_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_ov50_rst_en <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_uv50_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_uv50_rst_en <= wdata[6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_bg_otp_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_bg_otp_rst_en <= wdata[7];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_ldo15oc_rst_en <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_ldo15oc_rst_en <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_vt_rst_enable_iwdg <= 1'h0;
    else if (wren_vt_rst_enable) begin
        ff_vt_rst_enable_iwdg <= wdata[9];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_ov15_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_ov15_int_en <= wdata[2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_uv15_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_uv15_int_en <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_ov50_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_ov50_int_en <= wdata[5];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_uv50_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_uv50_int_en <= wdata[6];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_bg_otp_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_bg_otp_int_en <= wdata[7];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_enable_ldp15oc_int_en <= 1'h0;
    else if (wren_int_enable) begin
        ff_int_enable_ldp15oc_int_en <= wdata[8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_ov15_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_ov15_int_clr <= wdata[2];
    else 
        ff_int_clear_ov15_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_uv15_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_uv15_int_clr <= wdata[3];
    else 
        ff_int_clear_uv15_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_ov50_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_ov50_int_clr <= wdata[5];
    else 
        ff_int_clear_ov50_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_uv50_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_uv50_int_clr <= wdata[6];
    else 
        ff_int_clear_uv50_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_bg_otp_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_bg_otp_int_clr <= wdata[7];
    else 
        ff_int_clear_bg_otp_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_int_clear_ldo15oc_int_clr <= 1'h0;
    else if (wren_int_clear)
        ff_int_clear_ldo15oc_int_clr <= wdata[8];
    else 
        ff_int_clear_ldo15oc_int_clr <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_bias_cfg_d2a_ibias_en <= 1'h1;
    else if (wren_bias_cfg) begin
        ff_bias_cfg_d2a_ibias_en <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ssc_cfg_ssc_mode <= 2'h0;
    else if (wren_ssc_cfg) begin
        ff_ssc_cfg_ssc_mode <= wdata[1:0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ssc_cfg_ssc_en <= 1'h0;
    else if (wren_ssc_cfg) begin
        ff_ssc_cfg_ssc_en <= wdata[3];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ssc_cfg_ssc_freq_step <= 4'h1;
    else if (wren_ssc_cfg) begin
        ff_ssc_cfg_ssc_freq_step <= wdata[7:4];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ssc_cfg_ssc_freq_range <= 4'h8;
    else if (wren_ssc_cfg) begin
        ff_ssc_cfg_ssc_freq_range <= wdata[11:8];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ssc_cfg_ssc_freq_stay <= 7'h10;
    else if (wren_ssc_cfg) begin
        ff_ssc_cfg_ssc_freq_stay <= wdata[22:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_osc_dbg_sel <= 1'h0;
    else if (wren_clk_mux) begin
        ff_clk_mux_osc_dbg_sel <= wdata[0];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_lin_baud_clk_sel <= 1'h0;
    else if (wren_clk_mux) begin
        ff_clk_mux_lin_baud_clk_sel <= wdata[1];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_dbg_clk_sel <= 2'h0;
    else if (wren_clk_mux) begin
        ff_clk_mux_dbg_clk_sel <= wdata[3:2];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_adc_div <= 2'h0;
    else if (wren_clk_mux) begin
        ff_clk_mux_adc_div <= wdata[17:16];
    end
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_adc_div_up <= 1'h0;
    else if (wren_clk_mux)
        ff_clk_mux_adc_div_up <= wdata[20];
    else 
        ff_clk_mux_adc_div_up <= 1'h0;
end

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_clk_mux_adc_clk_sel <= 1'h0;
    else if (wren_clk_mux) begin
        ff_clk_mux_adc_clk_sel <= wdata[21];
    end
end


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------

wire  [31:0]  wir_r_clk_div  = {17'h0, wir_clk_div_css_flag, ff_clk_div_css_en, 3'h0, ff_clk_div_pclk_div[9:8], 1'h0, ff_clk_div_clksel[6:5], 1'h0, ff_clk_div_clk_div_factor[3:0]};
wire  [31:0]  wir_r_clk_gate_apb= {14'h0, ff_clk_gate_apb_clk_en_dflash, ff_clk_gate_apb_clk_en_iwdg, ff_clk_gate_apb_clk_en_can, 1'h0, ff_clk_gate_apb_clk_en_ediag, ff_clk_gate_apb_clk_en_ecap, ff_clk_gate_apb_clk_en_epwm, ff_clk_gate_apb_clk_en_spi1, ff_clk_gate_apb_clk_en_spi0, ff_clk_gate_apb_clk_en_adc1, ff_clk_gate_apb_clk_en_adc0, 1'h0, ff_clk_gate_apb_clk_en_sysctrl, ff_clk_gate_apb_clk_en_tim0, ff_clk_gate_apb_clk_en_tim1, ff_clk_gate_apb_clk_en_tim2, ff_clk_gate_apb_clk_en_uart0, 1'h0};
wire  [31:0]  wir_r_clk_gate_ahb= {29'h0, ff_clk_gate_ahb_clk_en_esci, ff_clk_gate_ahb_clk_en_dma, ff_clk_gate_ahb_clk_en_gpio};
wire  [31:0]  wir_r_system_software_reset= {31'h0, ff_system_software_reset_sys_sw_rst};
wire  [31:0]  wir_r_module_sw_reset_apb= {14'h0, ff_module_sw_reset_apb_sw_rst_dflash, ff_module_sw_reset_apb_sw_rst_iwdg, ff_module_sw_reset_apb_sw_rst_can0, 1'h0, ff_module_sw_reset_apb_sw_rst_ediag, ff_module_sw_reset_apb_sw_rst_ecap, ff_module_sw_reset_apb_sw_rst_epwm, ff_module_sw_reset_apb_sw_rst_spi1, ff_module_sw_reset_apb_sw_rst_spi0, ff_module_sw_reset_apb_sw_rst_adc1, ff_module_sw_reset_apb_sw_rst_adc0, 1'h0, ff_module_sw_reset_apb_sw_rst_sysctrl, ff_module_sw_reset_apb_sw_rst_tim0, ff_module_sw_reset_apb_sw_rst_tim1, ff_module_sw_reset_apb_sw_rst_tim2, ff_module_sw_reset_apb_sw_rst_uart0, ff_module_sw_reset_apb_sw_rst_wwdg};
wire  [31:0]  wir_r_module_sw_reset_ahb= {29'h0, ff_module_sw_reset_ahb_sw_rst_esci, ff_module_sw_reset_ahb_sw_rst_dma, ff_module_sw_reset_ahb_sw_rst_gpio};
wire  [31:0]  wir_r_pll_cfg1 = {ff_pll_cfg1_pll_ref_div[31:30], 6'h0, ff_pll_cfg1_pll_loopdiv[23:16], 6'h0, ff_pll_cfg1_pll_prediv[9:8], 2'h0, ff_pll_cfg1_pll_postdiv[5:4], 1'h0, ff_pll_cfg1_pll_ref_sel, wir_pll_cfg1_pll_stable, ff_pll_cfg1_pll_en};
wire  [31:0]  wir_r_pll_cfg2 = {1'h0, ff_pll_cfg2_pll_ldovrefsel[30:28], 2'h0, ff_pll_cfg2_pll_ckusable_divsel[25:16], 2'h0, ff_pll_cfg2_pll_icp[13:10], ff_pll_cfg2_pll_ccoband, ff_pll_cfg2_pll_kvco, 4'h0, ff_pll_cfg2_pll_lpf_rsel[3:1], ff_pll_cfg2_pll_lpf_c};
wire  [31:0]  wir_r_pll_dbg  = {wir_pll_dbg_pll_dbg_out, 12'h0, ff_pll_dbg_pll_ana_dbg[18:16], 13'h0, ff_pll_dbg_pll_dig_dbg[2:0]};
wire  [31:0]  wir_r_cir      = {23'h0, wir_cir_pll_stablt_int_flag, 7'h0, ff_cir_pll_ie};
wire  [31:0]  wir_r_extal_cfg= {30'h0, ff_extal_cfg_out_en, ff_extal_cfg_in_en};
wire  [31:0]  wir_r_rst_reason= {28'h0, wir_rst_reason_rst_reason_status[3:0]};
wire  [31:0]  wir_r_ldo1p5_cfg= {21'h0, ff_ldo1p5_cfg_d2a_ov15_level[10:8], 1'h0, ff_ldo1p5_cfg_d2a_uv15_level[6:4], 2'h0, ff_ldo1p5_cfg_d2a_ov15_en, ff_ldo1p5_cfg_d2a_uv15_en};
wire  [31:0]  wir_r_ldo5p0_cfg= {21'h0, ff_ldo5p0_cfg_d2a_ov50_level[10:8], 1'h0, ff_ldo5p0_cfg_d2a_uv50_level[6:4], 1'h0, ff_ldo5p0_cfg_d2a_en_test_avdd50_div, ff_ldo5p0_cfg_d2a_ov50_en, ff_ldo5p0_cfg_d2a_uv50_en};
wire  [31:0]  wir_r_bg_otp_cfg= {24'h0, ff_bg_otp_cfg_d2a_otp_sel[7:4], 2'h0, ff_bg_otp_cfg_d2a_bg_bf_en, ff_bg_otp_cfg_d2a_otp_en};
wire  [31:0]  wir_r_vt_rst_enable= {22'h0, ff_vt_rst_enable_iwdg, ff_vt_rst_enable_ldo15oc_rst_en, ff_vt_rst_enable_bg_otp_rst_en, ff_vt_rst_enable_uv50_rst_en, ff_vt_rst_enable_ov50_rst_en, ff_vt_rst_enable_otp_rst_en, ff_vt_rst_enable_uv15_rst_en, ff_vt_rst_enable_ov15_rst_en, 2'h0};
wire  [31:0]  wir_r_int_status= {23'h0, wir_int_status_ldo15oc_otp_lv, wir_int_status_bg_otp_lv, wir_int_status_uv50_lv, wir_int_status_ov50_lv, 1'h0, wir_int_status_uv15_lv, wir_int_status_ov15_lv, 2'h0};
wire  [31:0]  wir_r_int_enable= {23'h0, ff_int_enable_ldp15oc_int_en, ff_int_enable_bg_otp_int_en, ff_int_enable_uv50_int_en, ff_int_enable_ov50_int_en, 1'h0, ff_int_enable_uv15_int_en, ff_int_enable_ov15_int_en, 2'h0};
wire  [31:0]  wir_r_bias_cfg = {31'h0, ff_bias_cfg_d2a_ibias_en};
wire  [31:0]  wir_r_ssc_cfg  = {9'h0, ff_ssc_cfg_ssc_freq_stay[22:16], 4'h0, ff_ssc_cfg_ssc_freq_range[11:8], ff_ssc_cfg_ssc_freq_step[7:4], ff_ssc_cfg_ssc_en, 1'h0, ff_ssc_cfg_ssc_mode[1:0]};
wire  [31:0]  wir_r_clk_mux  = {10'h0, ff_clk_mux_adc_clk_sel, 3'h0, ff_clk_mux_adc_div[17:16], 12'h0, ff_clk_mux_dbg_clk_sel[3:2], ff_clk_mux_lin_baud_clk_sel, ff_clk_mux_osc_dbg_sel};

always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            10'b0000000000     :    ff_rdata = wir_r_clk_div;
            10'b0000000001     :    ff_rdata = wir_r_clk_gate_apb;
            10'b0000000011     :    ff_rdata = wir_r_clk_gate_ahb;
            10'b0000000101     :    ff_rdata = wir_r_system_software_reset;
            10'b0000000111     :    ff_rdata = wir_r_module_sw_reset_apb;
            10'b0000001001     :    ff_rdata = wir_r_module_sw_reset_ahb;
            10'b0000010000     :    ff_rdata = wir_r_pll_cfg1;
            10'b0000010001     :    ff_rdata = wir_r_pll_cfg2;
            10'b0000010010     :    ff_rdata = wir_r_pll_dbg;
            10'b0000011000     :    ff_rdata = wir_r_cir;
            10'b0000011100     :    ff_rdata = wir_r_extal_cfg;
            10'b0001000010     :    ff_rdata = wir_r_rst_reason;
            10'b0001000100     :    ff_rdata = wir_r_ldo1p5_cfg;
            10'b0001000110     :    ff_rdata = wir_r_ldo5p0_cfg;
            10'b0001000111     :    ff_rdata = wir_r_bg_otp_cfg;
            10'b0001001000     :    ff_rdata = wir_r_vt_rst_enable;
            10'b0001001001     :    ff_rdata = wir_r_int_status;
            10'b0001001010     :    ff_rdata = wir_r_int_enable;
            10'b0001001100     :    ff_rdata = wir_r_bias_cfg;
            10'b0010000000     :    ff_rdata = wir_r_ssc_cfg;
            10'b0001100000     :    ff_rdata = wir_r_clk_mux;
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
assign  clk_div_clk_div_factor= ff_clk_div_clk_div_factor;
assign  clk_div_clksel      = ff_clk_div_clksel   ;
assign  clk_div_pclk_div    = ff_clk_div_pclk_div ;
assign  clk_div_css_en      = ff_clk_div_css_en   ;
assign  clk_gate_apb_clk_en_uart0= ff_clk_gate_apb_clk_en_uart0;
assign  clk_gate_apb_clk_en_tim2= ff_clk_gate_apb_clk_en_tim2;
assign  clk_gate_apb_clk_en_tim1= ff_clk_gate_apb_clk_en_tim1;
assign  clk_gate_apb_clk_en_tim0= ff_clk_gate_apb_clk_en_tim0;
assign  clk_gate_apb_clk_en_sysctrl= ff_clk_gate_apb_clk_en_sysctrl;
assign  clk_gate_apb_clk_en_adc0= ff_clk_gate_apb_clk_en_adc0;
assign  clk_gate_apb_clk_en_adc1= ff_clk_gate_apb_clk_en_adc1;
assign  clk_gate_apb_clk_en_spi0= ff_clk_gate_apb_clk_en_spi0;
assign  clk_gate_apb_clk_en_spi1= ff_clk_gate_apb_clk_en_spi1;
assign  clk_gate_apb_clk_en_epwm= ff_clk_gate_apb_clk_en_epwm;
assign  clk_gate_apb_clk_en_ecap= ff_clk_gate_apb_clk_en_ecap;
assign  clk_gate_apb_clk_en_ediag= ff_clk_gate_apb_clk_en_ediag;
assign  clk_gate_apb_clk_en_can= ff_clk_gate_apb_clk_en_can;
assign  clk_gate_apb_clk_en_iwdg= ff_clk_gate_apb_clk_en_iwdg;
assign  clk_gate_apb_clk_en_dflash= ff_clk_gate_apb_clk_en_dflash;
assign  clk_gate_ahb_clk_en_gpio= ff_clk_gate_ahb_clk_en_gpio;
assign  clk_gate_ahb_clk_en_dma= ff_clk_gate_ahb_clk_en_dma;
assign  clk_gate_ahb_clk_en_esci= ff_clk_gate_ahb_clk_en_esci;
assign  system_software_reset_sys_sw_rst= ff_system_software_reset_sys_sw_rst;
assign  system_software_reset_sys_sw_rst_en= ff_system_software_reset_sys_sw_rst_en;
assign  module_sw_reset_apb_sw_rst_wwdg= ff_module_sw_reset_apb_sw_rst_wwdg;
assign  module_sw_reset_apb_sw_rst_uart0= ff_module_sw_reset_apb_sw_rst_uart0;
assign  module_sw_reset_apb_sw_rst_tim2= ff_module_sw_reset_apb_sw_rst_tim2;
assign  module_sw_reset_apb_sw_rst_tim1= ff_module_sw_reset_apb_sw_rst_tim1;
assign  module_sw_reset_apb_sw_rst_tim0= ff_module_sw_reset_apb_sw_rst_tim0;
assign  module_sw_reset_apb_sw_rst_sysctrl= ff_module_sw_reset_apb_sw_rst_sysctrl;
assign  module_sw_reset_apb_sw_rst_adc0= ff_module_sw_reset_apb_sw_rst_adc0;
assign  module_sw_reset_apb_sw_rst_adc1= ff_module_sw_reset_apb_sw_rst_adc1;
assign  module_sw_reset_apb_sw_rst_spi0= ff_module_sw_reset_apb_sw_rst_spi0;
assign  module_sw_reset_apb_sw_rst_spi1= ff_module_sw_reset_apb_sw_rst_spi1;
assign  module_sw_reset_apb_sw_rst_epwm= ff_module_sw_reset_apb_sw_rst_epwm;
assign  module_sw_reset_apb_sw_rst_ecap= ff_module_sw_reset_apb_sw_rst_ecap;
assign  module_sw_reset_apb_sw_rst_ediag= ff_module_sw_reset_apb_sw_rst_ediag;
assign  module_sw_reset_apb_sw_rst_can0= ff_module_sw_reset_apb_sw_rst_can0;
assign  module_sw_reset_apb_sw_rst_iwdg= ff_module_sw_reset_apb_sw_rst_iwdg;
assign  module_sw_reset_apb_sw_rst_dflash= ff_module_sw_reset_apb_sw_rst_dflash;
assign  module_sw_reset_ahb_sw_rst_gpio= ff_module_sw_reset_ahb_sw_rst_gpio;
assign  module_sw_reset_ahb_sw_rst_dma= ff_module_sw_reset_ahb_sw_rst_dma;
assign  module_sw_reset_ahb_sw_rst_esci= ff_module_sw_reset_ahb_sw_rst_esci;
assign  pll_cfg1_pll_en     = ff_pll_cfg1_pll_en  ;
assign  pll_cfg1_pll_ref_sel= ff_pll_cfg1_pll_ref_sel;
assign  pll_cfg1_pll_postdiv= ff_pll_cfg1_pll_postdiv;
assign  pll_cfg1_pll_prediv = ff_pll_cfg1_pll_prediv;
assign  pll_cfg1_pll_loopdiv= ff_pll_cfg1_pll_loopdiv;
assign  pll_cfg1_pll_ref_div= ff_pll_cfg1_pll_ref_div;
assign  pll_cfg2_pll_lpf_c  = ff_pll_cfg2_pll_lpf_c;
assign  pll_cfg2_pll_lpf_rsel= ff_pll_cfg2_pll_lpf_rsel;
assign  pll_cfg2_pll_kvco   = ff_pll_cfg2_pll_kvco;
assign  pll_cfg2_pll_ccoband= ff_pll_cfg2_pll_ccoband;
assign  pll_cfg2_pll_icp    = ff_pll_cfg2_pll_icp ;
assign  pll_cfg2_pll_ckusable_divsel= ff_pll_cfg2_pll_ckusable_divsel;
assign  pll_cfg2_pll_ldovrefsel= ff_pll_cfg2_pll_ldovrefsel;
assign  pll_dbg_pll_dig_dbg = ff_pll_dbg_pll_dig_dbg;
assign  pll_dbg_pll_ana_dbg = ff_pll_dbg_pll_ana_dbg;
assign  cir_pll_ie          = ff_cir_pll_ie       ;
assign  cir_pll_stablt_int_clr= ff_cir_pll_stablt_int_clr;
assign  extal_cfg_in_en     = ff_extal_cfg_in_en  ;
assign  extal_cfg_out_en    = ff_extal_cfg_out_en ;
assign  extal_cfg_stg       = ff_extal_cfg_stg    ;
assign  ldo1p5_cfg_d2a_uv15_en= ff_ldo1p5_cfg_d2a_uv15_en;
assign  ldo1p5_cfg_d2a_ov15_en= ff_ldo1p5_cfg_d2a_ov15_en;
assign  ldo1p5_cfg_d2a_uv15_level= ff_ldo1p5_cfg_d2a_uv15_level;
assign  ldo1p5_cfg_d2a_ov15_level= ff_ldo1p5_cfg_d2a_ov15_level;
assign  ldo5p0_cfg_d2a_uv50_en= ff_ldo5p0_cfg_d2a_uv50_en;
assign  ldo5p0_cfg_d2a_ov50_en= ff_ldo5p0_cfg_d2a_ov50_en;
assign  ldo5p0_cfg_d2a_en_test_avdd50_div= ff_ldo5p0_cfg_d2a_en_test_avdd50_div;
assign  ldo5p0_cfg_d2a_uv50_level= ff_ldo5p0_cfg_d2a_uv50_level;
assign  ldo5p0_cfg_d2a_ov50_level= ff_ldo5p0_cfg_d2a_ov50_level;
assign  bg_otp_cfg_d2a_otp_en= ff_bg_otp_cfg_d2a_otp_en;
assign  bg_otp_cfg_d2a_bg_bf_en= ff_bg_otp_cfg_d2a_bg_bf_en;
assign  bg_otp_cfg_d2a_otp_sel= ff_bg_otp_cfg_d2a_otp_sel;
assign  vt_rst_enable_ov15_rst_en= ff_vt_rst_enable_ov15_rst_en;
assign  vt_rst_enable_uv15_rst_en= ff_vt_rst_enable_uv15_rst_en;
assign  vt_rst_enable_otp_rst_en= ff_vt_rst_enable_otp_rst_en;
assign  vt_rst_enable_ov50_rst_en= ff_vt_rst_enable_ov50_rst_en;
assign  vt_rst_enable_uv50_rst_en= ff_vt_rst_enable_uv50_rst_en;
assign  vt_rst_enable_bg_otp_rst_en= ff_vt_rst_enable_bg_otp_rst_en;
assign  vt_rst_enable_ldo15oc_rst_en= ff_vt_rst_enable_ldo15oc_rst_en;
assign  vt_rst_enable_iwdg  = ff_vt_rst_enable_iwdg;
assign  int_enable_ov15_int_en= ff_int_enable_ov15_int_en;
assign  int_enable_uv15_int_en= ff_int_enable_uv15_int_en;
assign  int_enable_ov50_int_en= ff_int_enable_ov50_int_en;
assign  int_enable_uv50_int_en= ff_int_enable_uv50_int_en;
assign  int_enable_bg_otp_int_en= ff_int_enable_bg_otp_int_en;
assign  int_enable_ldp15oc_int_en= ff_int_enable_ldp15oc_int_en;
assign  int_clear_ov15_int_clr= ff_int_clear_ov15_int_clr;
assign  int_clear_uv15_int_clr= ff_int_clear_uv15_int_clr;
assign  int_clear_ov50_int_clr= ff_int_clear_ov50_int_clr;
assign  int_clear_uv50_int_clr= ff_int_clear_uv50_int_clr;
assign  int_clear_bg_otp_int_clr= ff_int_clear_bg_otp_int_clr;
assign  int_clear_ldo15oc_int_clr= ff_int_clear_ldo15oc_int_clr;
assign  bias_cfg_d2a_ibias_en= ff_bias_cfg_d2a_ibias_en;
assign  ssc_cfg_ssc_mode    = ff_ssc_cfg_ssc_mode ;
assign  ssc_cfg_ssc_en      = ff_ssc_cfg_ssc_en   ;
assign  ssc_cfg_ssc_freq_step= ff_ssc_cfg_ssc_freq_step;
assign  ssc_cfg_ssc_freq_range= ff_ssc_cfg_ssc_freq_range;
assign  ssc_cfg_ssc_freq_stay= ff_ssc_cfg_ssc_freq_stay;
assign  clk_mux_osc_dbg_sel = ff_clk_mux_osc_dbg_sel;
assign  clk_mux_lin_baud_clk_sel= ff_clk_mux_lin_baud_clk_sel;
assign  clk_mux_dbg_clk_sel = ff_clk_mux_dbg_clk_sel;
assign  clk_mux_adc_div     = ff_clk_mux_adc_div  ;
assign  clk_mux_adc_div_up  = ff_clk_mux_adc_div_up;
assign  clk_mux_adc_clk_sel = ff_clk_mux_adc_clk_sel;
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
